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RFG50N05L, RFP50N05L
Data Sheet July 1999 File Number
2424.3
50A, 50V, 0.022 Ohm, Logic Level, N-Channel Power MOSFETs
These are logic-level N-channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use with logic-level (5V) driving sources in applications such as programmable controllers, automotive switching, switching regulators, switching converters, motor relay drivers and emitter switches for bipolar transistors. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate bias in the 3V - 5V range, thereby facilitating true on-off power control directly from integrated circuit supply voltages. Formerly developmental type TA09872.
Features
* 50A, 50V * rDS(ON) = 0.022 * UIS SOA Rating Curve (Single Pulse) * Design Optimized for 5V Gate Drive * Can be Driven Directly from CMOS, NMOS, TTL Circuits * Compatible with Automotive Drive Requirements * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Majority Carrier Device * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RFG50N05L RFP50N05L PACKAGE TO-247 TO-220AB BRAND RFG50N05L RFP50N05L
Symbol
D
NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in the tape and reel, i.e., RFP50N05L9A.
G
S
Packaging
JEDEC STYLE TO-247
SOURCE DRAIN GATE DRAIN (BOTTOM SIDE METAL) DRAIN (FLANGE)
JEDEC TO-220AB
SOURCE DRAIN GATE
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RFG50N05L, RFP50N05L
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RFG50N05L Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Above TC = 25oC, Derate Linearly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 50 50 50 130 10 110 0.88 RFP50N05L 50 50 50 130 10 110 0.88 UNITS V V A A V W W/oC oC oC oC
Refer to UIS SOA Curve -55 to 150 300 260 -55 to 150 300 260
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V (Figure 10) VGS = VDS, ID = 250A (Figure 9) VDS = Rated BVDSS, VGS = 0 VDS = 0.8 x Rated BVDSS, VGS = 0, TC = 150oC MIN 50 1 VGS = 0 to 10V VGS = 0 to 5V VGS = 0 to 1V VDD = 40V, ID = 50A RL = 0.8 (Figures 17, 18) TYP 15 50 50 15 MAX 2 25 250 100 0.022 0.027 100 100 140 80 6 1.14 80 UNITS V V A A nA ns ns ns ns ns ns nC nC nC
oC/W oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance (Note 2)
IGSS rDS(ON)
VGS = 10V, VDS = 0V ID = 50A, VGS = 5V (Figure 7) ID = 50A, VGS = 4V
Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
t(ON) tD(ON) tr tD(OFF) tf t(OFF) QG(TOT) QG(5) QG(th) RJC RJA
VGS = 5V, RGS = 2.5, RL = 1 (Figures 12, 15, 16)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time NOTES: 2. Pulsed: pulse duration = 300s maximum, duty cycle = 2%. 3. Repititive rating: pulse width limited by maximum junction temperature. SYMBOL VSD trr ISD = 50A ISD = 50A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.5 1.25 UNITS V ns
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RFG50N05L, RFP50N05L Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC) ID, DRAIN CURRENT (A) 50
40
30
20
10
0 25
50
75
100
125
150
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
100 IDS, DRAIN TO SOURCE CURRENT (A)
ID MAX CONTINUOUS
DC OPERATION 10 OPERATION IN THIS AREA LIMITED BY rDS(ON) 1
IAS, AVALANCHE CURRENT (A)
TC = 25oC TJ = MAX RATED
1000
IF R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) IF R = 0 TAV = (L/R) IN [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
IDM
100 STARTING TJ = 25oC
STARTING TJ = 150oC
0.1 1
10 VDS, DRAIN TO SOURCE VOLTAGE (V)
100
10 0.01
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SAFE OPERATING AREA
ID(ON), DRAIN TO SOURCE CURRENT (A)
140 IDS, DRAIN TO SOURCE CURRENT (A) 120 100 80 60 40 20 VGS = 2V 0 0 1.5 3.0 4.5 6.0 7.5 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = 3V VGS = 10V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. TC - 25oC VGS = 5V
140 120 100 VDS = 15V 80 60 40 20 0 0 1.5 3.0 4.5 6.0 7.5 VGS, GATE TO SOURCE VOLTAGE (V) -55oC 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. TC - 25oC 150oC
VGS = 4V
FIGURE 5. SATURATION CHARACTERISTICS
FIGURE 6. TRANSFER CHARACTERISTICS
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RFG50N05L, RFP50N05L Typical Performance Curves
3.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.5 2.0 1.5 1.0 0.5 0 -50 0 50 100 150 TJ, JUNCTION TEMPERATURE (oC) NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. VGS = 5V ID = 50A
(Continued)
2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. ID = 50A, VGS = 5V
1.5
1.2
0.8
0.4
0 4 5 6 VGS, GATE TO SOURCE VOLTAGE (V) 7
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
2.0
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE
2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
VGS = VDS, ID = 250A 1.8 NORMALIZED GATE THRESHOLD VOLTAGE
ID = 250A 1.8
1.2
1.2
0.8
0.8
0.4
0.4
0 -50
0 50 100 TJ, JUNCTION TEMPERATURE (oC)
150
0 -50
0
50
100
150
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
50 DRAIN TO SOURCE VOLTAGE (V) 10 GATE TO SOURCE VOLTAGE (V)
6000 5000 C, CAPACITANCE (pF) 4000 3000 2000 COSS 1000 CRSS 0 0 5 10 15 20 25 VDS, DRAIN TO SOURCE (V) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD CISS
RL = 0 IG(REF) = 1.25mA
37.5 VDD = BVDSS 25 0.75BVDSS VDD = BVDSS 0.75BVDSS GATE TO SOURCE VOLTAGE 0.50BVDSS 5
12.5
0.50BVDSS 0.25BVDSS 0.25BVDSS DRAIN TO SOURCE VOLTAGE 0 20 IG(REF) IG(ACT) TIME-MICROSECONDS 80 IG(REF) IG(ACT) 0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
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RFG50N05L, RFP50N05L Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 14. UNCLAMPED ENERGY WAVEFORMS
tON VDS VDS VGS RL
+
tOFF td(OFF) tr tf 90%
td(ON)
90%
DUT RGS VGS
-
VDD
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 15. SWITCHING TIME TEST CIRCUIT
FIGURE 16. RESISTIVE SWITCHING WAVEFORMS
VDS RL VDD VDS VGS = 10V VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) IG(REF) 0 VGS = 5V
DUT IG(REF)
FIGURE 17. GATE CHARGE TEST CIRCUIT
FIGURE 18. GATE CHARGE WAVEFORMS
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RFG50N05L, RFP50N05L
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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